June 16, 2024

Cadence 2024 Hiring Freshers as Design Engineer

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Cadence Recruitment Drive for 2024 Freshers

About Company : Cadence is a leading IT solutions provider, offering Applications, Business Process Outsourcing and Infrastructure services globally through a combination of technology knowhow, domain and process expertise. Over the years we have left an indelible impression in the IT solutions domain with an impressive clientele and an extensive global presence. The accolades we have been garnering can be attributed to our undeterred focus in delivering quality solutions across verticals that meet the challenging requirements of our esteemed customers.

Company Full Name : Cadence
Job Role : Design Engineer
Degree Needed : BE/BTech/ME/MTech
Batch : Any Batch
Location : Bangalore

Job Description :
Roles and Responsibility : 

  • Pre-silicon emulation and Verification of System in NCSIM and Palladium.
  • Hardware and Subsystem Design for all the Projects. (HW/SW infrastructure designed within the team.)
  • Prototyping and Firmware Development for our High-Speed Serdes like PCIe, CXL, UCIe, USB, and ethernet.
  • Lead the Bringup, Debug, Compliance efforts, and System level Characterization all the way to report release.
  • Engage in interop and Customer Debug.
  • Chance to work on cutting-edge SERDES IPs from Cadence. Refer to Cadence’s Website for more details on our SERDES IPs.
  • Tremendous learning curve on SERDES PHY, Controllers, Protocol, and System integration.
  • Hardware and Subsystem design expertise.
  • The Kick in deploying and debugging your Solutions in different System environments.

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Required Qualification and Skills : 

To be eligible for this position, you should meet the following requirements:

  • 1-3 years (with Btech) or 0-2 years (with Mtech) experience in Post-Silicon PHY and Systems Validation.
  • Physical Layer and Protocol layer experience on At least one High-speed SERDES.
  • Debug skills.
  • Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, and Analyzers.
  • Experience leading System validation efforts for SERDES solutions.
  • Experience in PCIe LTSSM states is a plus.
  • Experience in FPGA Design and Schematic design.
  • Experience in IP/SoC Physical Layer Electrical Validation experience.
  • Familiarity with Verilog RTL coding, FPGA coding, python, C/C++
  • Candidates are expected to be passionate about analog and digital electronic circuit design.

How to Apply For Cadence Recruitment Drive 2024 ?

All interested and eligible candidates can apply for this position online via the following link as soon as possible.

Apply link : Click Here

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