June 22, 2024

Digital Electronics and Microprocessor

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Digital Electronics and Microprocessor Question and Answers

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Q1. A) List out the contents of all the registers including the flag register (flag bits) and status immediately after the 8086 processor undergoes a hard reset.
B) Why is it that the 8086 processor is generally made to execute a long jump instruction soon after hard reset?
C) If the long jump instruction after reset has an address F800:0000, which is to the starting of ROM memory, what is the amount of ROM memory available in the system?
D) What is one significant advantage of having memory segmentation?

Ans – A) After a hard reset of the 8086 processor, all the registers, including the flag register (FLAGS), will be initialized to their default values. Here’s a list of the contents of the registers and flags immediately after a hard reset:

  1. Data Registers (AX, BX, CX, DX):
    • AX (Accumulator): 0000H
    • BX (Base): 0000H
    • CX (Count): 0000H
    • DX (Data): 0000H
  2. Pointer and Index Registers (SP, BP, SI, DI):
    • SP (Stack Pointer): FFFFH
    • BP (Base Pointer): 0000H
    • SI (Source Index): 0000H
    • DI (Destination Index): 0000H
  3. Segment Registers (CS, DS, ES, SS):
    • CS (Code Segment): FFFFH
    • DS (Data Segment): FFFFH
    • ES (Extra Segment): FFFFH
    • SS (Stack Segment): FFFFH
  4. Instruction Pointer (IP):
    • IP: 0000H
  5. Flag Register (FLAGS):
    • Flags (Status Bits):
      • Carry Flag (CF): 0
      • Parity Flag (PF): 0
      • Auxiliary Carry Flag (AF): 0
      • Zero Flag (ZF): 0
      • Sign Flag (SF): 0
      • Trap Flag (TF): 0
      • Interrupt Flag (IF): 0
      • Direction Flag (DF): 0
      • Overflow Flag (OF): 0

After a hard reset, the registers are typically set to zero or specific default values, and the flags are cleared.

B) The idea of executing a long jump instruction soon after a hard reset of the 8086 processor is often associated with the process of initializing the system and setting up the initial state for the program execution. This is commonly referred to as a “reset vector” or “reset handler.”

Here are some reasons why a long jump instruction might be used after a hard reset:

  1. Setting the Program Counter (PC): After a hard reset, the contents of the instruction pointer (IP) register are typically set to a specific memory location known as the reset vector. The reset vector points to the starting address of the initialization code. Executing a long jump instruction (like LJMP in assembly) allows the processor to jump to a specific memory address and begin execution from there.
  2. Initializing Code and Data Segments: The initialization code at the reset vector is responsible for setting up the initial state of the system, initializing memory, configuring data segments, and performing other essential tasks before handing control over to the main program. A long jump instruction may be used to transition from the initial setup code to the main program.
  3. Ensuring a Known State: Executing a long jump allows for precise control over the initial program state. It helps ensure that the processor starts executing instructions from a known and predetermined location, providing a standardized starting point for the system.
  4. Supporting Interrupt Handling: By setting up the interrupt vector table and other essential structures during the initialization process, the system becomes prepared to handle interrupts and exceptions effectively. This is crucial for the proper functioning of an operating system or any software running on the 8086 processor.

C) In the Intel 8086 architecture, the address space is segmented, and each segment can address up to 64 KB (kilobytes) of memory. The long jump instruction address you provided, F800:0000, indicates a segment of F800H and an offset of 0000H.To calculate the absolute memory address, you can use the formula:

Physical Address=(Segment×16)+Offset

Substitute the values:

Convert F800H to decimal:

So, the physical address is 63488. This is the starting address of the ROM memory.

To find the amount of ROM memory available, we need to know the size of each segment. In the 8086 architecture, each segment can address 64 KB (kilobytes) of memory. Therefore, the amount of ROM memory available in the system is 64 KB.

D) One significant advantage of memory segmentation in architectures like the Intel 8086 is the ability to organize and manage memory in a flexible and modular way. Here are some key advantages:

  1. Modularity and Code Organization:
    • Memory segmentation allows for the division of the address space into segments, providing a modular structure. Each segment can be dedicated to specific functions or types of data.
    • Segmentation helps in organizing code and data into logical units, making it easier for programmers to manage and understand the structure of a program.
  2. Support for Large Address Spaces:
    • Segmentation allows the processor to access a larger address space by combining a 16-bit segment register with a 16-bit offset. This results in a 20-bit physical address, providing access to a total of 1 MB of memory.
    • Without segmentation, a purely 16-bit architecture would be limited to addressing only 64 KB directly.
  3. Memory Protection:
    • Segmentation enables the implementation of memory protection mechanisms. Each segment can have its own access permissions, allowing the operating system to control read, write, and execute permissions on a per-segment basis.
    • This helps prevent unintended access or modification of critical system data and code.
  4. Dynamic Memory Allocation:
    • Segmentation facilitates dynamic memory allocation and deallocation. Segments can be created and resized as needed, allowing for more flexible memory management.
    • This is particularly useful for high-level programming languages and dynamic data structures.
  5. Shared Memory and Interprocess Communication:
    • Segmentation allows different segments to overlap, facilitating shared memory spaces. This is beneficial for interprocess communication, as multiple processes can share data through common segments.
    • Shared memory is advantageous for efficient communication between processes without the need for complex data transfer mechanisms.
  6. Code Reusability:

    • Segmentation supports code reusability by allowing different programs or modules to be stored in separate segments. This modularity makes it easier to reuse and link code components in various applications.

Q2. Design a synchronous modulo-5 counter using JK-flip flop which counts through the stages given 0 to 1 to 5 to 7 to 6 to 0 and repeats.

Ans – To design a synchronous modulo-5 counter using JK flip-flops that counts through the specified sequence (0, 1, 5, 7, 6, 0) and repeats, we need to create a state transition table and then implement the JK flip-flop circuit accordingly. Let’s use a 3-bit counter to represent the states.

Here’s the state transition table:

In the table, the columns represent the current state, the next state, and the JK inputs for the flip-flops. The next state values are in binary, and JK inputs are given based on the desired sequence.

Now, let’s design the JK flip-flop circuit. We’ll use three JK flip-flops (FF1, FF2, and FF3) to represent the three bits of the counter.

  • Connect the J and K inputs of FF1, FF2, and FF3 according to the JK input values in the table.
  • Connect the clock (C) input of all flip-flops together.
  • Use the Q outputs of FF1, FF2, and FF3 as the three output bits (Q2, Q1, Q0) of the counter.

Here’s a textual representation of the circuit:

Connect the JK inputs and clock as follows:

  • JK inputs for FF1: J1 = 0, K1 = 1
  • JK inputs for FF2: J2 = 1, K2 = 0
  • JK inputs for FF3: J3 = 1, K3 = 1
  • Connect the clock (CLK) input to the clock signal.

Q3. Use a stack map to show the effect of each of the following instructions on the stack pointer and on the contents of the stack. Name the registers that are going to reside in Stack


A stack is often used to store temporary data and manage subroutine calls. The stack pointer (SP) is a register that points to the top of the stack. Let’s use a hypothetical assembly-like language to illustrate the effects of certain instructions on the stack. We’ll assume there’s a stack map that shows the state of the stack before and after each instruction.

Let’s use the following conventions:

  • SP: Stack Pointer
  • R1, R2, R3: General-purpose registers
  • [ ]: Value at the memory location

Initial Stack: [ ] (Empty Stack)

  1. PUSH R1
    • Before: [ ]
    • After: [R1]
    • SP: SP – 1
  2. PUSH R2
    • Before: [R1]
    • After: [R1, R2]
    • SP: SP – 1
  3. POP R3
    • Before: [R1, R2]
    • After: [R1]
    • R3: R2 (value popped from the stack)
    • SP: SP + 1
  4. PUSH R3
    • Before: [R1]
    • After: [R1, R3]
    • SP: SP – 1
  5. POP R2
    • Before: [R1, R3]
    • After: [R1]
    • R2: R3 (value popped from the stack)
    • SP: SP + 1

Q4. Construct the binary code for the instruction MOV CX, [BX]

Ans- The x86 assembly language instruction “MOV CX, [BX]” can be represented in binary code. Here’s the breakdown of the binary encoding:

  1. Opcode for MOV instruction:
    • The opcode for the MOV instruction is typically represented by the binary code 100010.
  2. ModR/M byte:
    • The ModR/M byte specifies the operand addressing mode and the registers involved in the instruction. For the MOV instruction with a memory operand, the ModR/M byte is constructed as follows:
      • Mod field: 00 (indicating a memory operand addressed by only the base register, BX).
      • Reg/Opcode field: 01 (indicating CX as the destination register).
      • R/M field: 011 (indicating BX as the base register).

    So, the ModR/M byte becomes 00011011 in binary.

  3. Displacement (Optional):
    • Since there is no displacement in this case (no immediate value or offset), this part is all zeros.

Putting it all together, the binary representation of the “MOV CX, [BX]” instruction is as follows:
10001000 00011011 00000000

Q5. Write an Assembly Language Program to search for a character in a given string and calculate the number of occurrences of the character in the given string (new)

Ans- x86 assembly language program using NASM syntax that searches for a character in a given string and calculates the number of occurrences of that character:

section .data
input_string db ‘This is a sample string.’, 0
search_char db ‘s’ ; Change this character to the one you want to search for
newline db 10 ; Newline character for printing

section .text
global _start

; Set registers
mov ecx, 0 ; Counter for the number of occurrences
mov esi, input_string ; Source index for the input string
mov al, search_char ; Character to search for

; Compare the current character with the search character
cmp byte [esi], al
je found_char

; If end of string is reached, exit the loop
cmp byte [esi], 0
je end_program

; Move to the next character in the string
inc esi
jmp search_loop

; Increment the counter for the number of occurrences
inc ecx

; Move to the next character in the string
inc esi
jmp search_loop

; Display the result
mov eax, 4 ; syscall: sys_write
mov ebx, 1 ; file descriptor: STDOUT
mov ecx, ecx ; number of occurrences
mov edx, 4 ; length of the message
mov esi, ecx ; pointer to the message
int 0x80 ; call kernel

; Exit the program
mov eax, 1 ; syscall: sys_exit
xor ebx, ebx ; status: 0
int 0x80 ; call kernel

Q6.Write an assembly language program to find the LCM of two numbers

Ans- Here’s a simple example of an x86 assembly language program to find the Least Common Multiple (LCM) of two numbers using the Euclidean algorithm. This example assumes that the input numbers are stored in memory at addresses num1 and num2:

section .data
num1 dd 12 ; Change these values as needed
num2 dd 18 ; Change these values as needed
result dd 0

section .text
global _start

; Load the numbers into registers
mov eax, [num1]
mov ebx, [num2]

; Calculate GCD using Euclidean algorithm
call find_gcd

; Calculate LCM using the formula: LCM(a, b) = (a * b) / GCD(a, b)
mov eax, [num1]
mul dword [num2]
div dword [result]

; The result is now in eax

; Exit the program
mov eax, 1 ; syscall number for exit
xor ebx, ebx ; exit code 0
int 0x80 ; make syscall

; Euclidean algorithm to find GCD
; Inputs: eax = num1, ebx = num2
; Outputs: result = GCD(num1, num2)

cmp ebx, 0
je .done

; Swap if necessary
mov edx, eax
mov eax, ebx
mov ebx, edx

; Calculate remainder
xor edx, edx
div ebx

; Save remainder for the next iteration
mov [result], edx

; Recursively call find_gcd
call find_gcd


Q7.a) Write the Control Word Register (CWR) format of a Programmable Peripheral device (8255A) interfacing with 8086 to work as an I/O port to initialize port A as input, port B as output, Port C upper as input and Port C lower as output. Use Mode 1 for group A and Mode 0 for group B. Address of CWR-43h. Assume CS’, WR’ of 8255A are both logical 0.

b) Write the initialization instruction using 8086 Microprocessor to ensure the above CWR of the 8255A.

Ans- a) The Control Word Register (CWR) format for the 8255A interfacing with 8086 is as follows:
| D7 | D6 | D5 | D4 | D3 |   D2 |     D1    | D0 |
|— -|— -|—–|—–|—–|——-|——–|—–|
| 1    | 0    | 0    | 0   | SC1 | SC0 | RW1 | RW0 |

  • SC1(SC0): 00 (Mode 0 for group B)
  • RW1(RW0): 01 (Mode 1 for group A)

So, the binary format for the Control Word to initialize port A as input, port B as output, Port C upper as input, and Port C lower as output is 00000101.

b) The initialization instruction using 8086 Microprocessor to set the above Control Word Register (CWR) of the 8255A at address 43h would be:
MOV AL, 00000101b ; Load the binary control word into AL
OUT 43h, AL ; Output AL to the control register at address 43h
This assumes that the CS’ and WR’ signals are already set to logical 0

Q8. A) Predict the state of the six 8086 conditional flags after each of the following instructions or group of instructions executes. Use the register contents shown in figure below. Assume that all flags are reset before the instructions execute. a. MOV AL, AH b. ADD BL,CL
B) Describe the operation and results of each of the following instructions, given the register content shown in figure above. Include in your answer the physical address or register that each instruction will get its operands from and the physical address or register that each instruction will put the result in. a. ROL AX,CL b. JMP BX c. ADD AX, [BX][SI]

Ans- A) a. MOV AL, AH: Copies the contents of AH to AL. No flags are affected. b. ADD BL, CL: Adds the contents of CL to BL. Flags affected: CF (Carry Flag), PF (Parity Flag), AF (Auxiliary Flag), ZF (Zero Flag), SF (Sign Flag), OF (Overflow Flag).

B) a. ROL AX, CL: Rotates the bits in AX left through the carry flag, the number of times specified in CL. Flags affected: CF, OF, SF, ZF, PF. b. JMP BX: Unconditional jump to the address specified in BX. c. ADD AX, [BX][SI]: Adds the word at the address formed by adding BX and SI to the contents of AX. Flags affected: CF, OF, SF, ZF, PF.

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