Computer Organization and Architecture MCQ Questions & Answers

Quiz – 3

1. For the program shown, what change should be made in the JEQ 28 instruction if one is using ADD #01, R02 for instruction INC R02?0000   0000   MOV #0,   R02
   0006   0006   STB R02, @R02
   0011   0011   CMP #63, R02
   0017   0017   JEQ 28
   0021   0021   INC R02
   0024   0024   JMP 6
   0028   0028   HLT
   Ans : JEQ 29
2. For the program shown below the STW instruction 5F will be in memory location.0000   0000   MOV #54,  R00
   0006   0006   MOV #95,  R01
   0012   0012   STB R00,  @R01
   0017   0017   MOV #24567,  R02
   0023   0023   MOV #86,  R04
   0029   0029   STW R02,  @R04
   Ans : 88
   
   
   
3. The instruction MOV #(a), R00, where “a” represents decimal number. What is the largest positive number that can be entered in the register?
   Ans : 32767
4. In which instruction the data hazard is identified and by with what colour?
   
   Ans : In Instruction 5 with yellow
5. The instruction MOV #(a), R05, where “a” represents decimal number. What is the smallest -ve number that can be entered in the register?
   Ans : -32768
   
   
   
6. For the given program direct mapping is used and we use two different cache configuration (A) Block size 4. Cache size 16 (B) Cache size remains the same, block size is 8. Find the correct statement from the options.0031   0031   LDB 4,  R03
   0037   0037   LDB 5,  R04
   0043   0043   LDB 6,  R05
   0049   0049   LDB 7,  R06
   0055   0055   LDB 8,  R07
   Ans : B has a higher miss than A
7. How many hits & misses will be encountered if the following code is executed once on the CPU when direct cache mapping is applied. Where the block size is 4 and the cache size is 16. Assume the data memory has already been loaded with some other program.0031   0031   LBD 4,  R03
   0037   0037   LDB 5,  R04
   0043   0043   LDB 6,  R05
   0049   0049   LDB 7,  R06
   0055   0055   LDB 8,  R07
   Ans : 0 hits and 5 misses
   
   
   
8. The following instruction is executed on the CPU simulator. What will be the content of R04 in HEX representation?0022   0022   MOV #85,  R04
   0028   0028   DIV #5,  R04
   Ans : FF17
9. A sequence of program instructions is shown below, Identify from the options given the difference in execution of STW, and STB.0000   0000   MOV #54,  ROO
   0006   0006   MOV #95,  R01
   0012   0012   STB R00, @R01
   0017   0017   MOV #24567,  R02
   0023   0023   MOV #86,  R04
   0029   0029   STW R02,  @R04
   Ans : STW occupies 2 memory locations in DADA memory, where as STB 4.
   
   
   
10. The figure shows the pipeline of a program written on the left with the command to the simulator” not to insert bubbles”. Then what will be the content of Register R03.
    
    Ans : 15
    
    
    

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Quiz – 2

1. If a cache has a capacity of 16 KB and line length of 128 bytes, how many sets does the cache have if it is 2-way set associative?
   Ans. 8
2. A processor executes 40,000,000 cycles in one second. A printer device is sent 16 bytes in programmed l/o mode. A printer can print 250 characters per second and does not have a print-buffer, how much time will be taken to acknowledge the character status?
   Ans. 16 processor time
3. A microprocessor scans the status of an output I/O device every 50 ms. This is accomplished by means of a timer alerting the processor every 50 ms. The interface of the device includes two ports: one for status and one for data output. How long does it take to scan and service the device given a clocking rate of 10 MHz? Assume for simplicity that all pertinent instruction cycles take 10 clock cycles
   Ans. 1 micro sec
   
   
   
4. A 1GHz system having miss penalty of 5 cycles and Hit time of 5cyles and Miss rate of 0%. Then what is Cycle time and Average Access time.
   Ans. 1ns, 5ns
5. If a processor scans the keyboard every 400 ms. How many times will the keyboard be checked in an 4-hour period?
   Ans. 36000
   
6. PSW is saved in stack when there is a
   Ans. interrupt recognised
   
   
   
7. if the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be
   Ans. 16 bits
8. if memory access takes 20 ns with cache and 110 ns with out it, then the ratio (cache uses a 10 ns memory) is
   Ans. 90%
   
   
   
9. In a program using subroutine call instruction, it is necessary to
   Ans. Clear the instruction register
10. If a cache has a capacity of 16 KB and line length of 128 bytes, how many sets does the cache have if it is 4-way set associative?
    Ans. 4
    
    
    

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